CR125A時(shí)鐘恢復(fù)儀器

主要特點(diǎn)和優(yōu)點(diǎn)

• 儀器級(jí)的時(shí)鐘恢復(fù)設(shè)備

• 150Mb/s 到28.6Gb/s 連續(xù)可調(diào)的時(shí)鐘恢復(fù)，覆蓋下一代IO標(biāo)準(zhǔn)，包括PCIe3.0、10GBASE-KR、16xFC、25/28G CEI和100GBASE-LR-4/100GBase-ER-4

• 從100KHz 到12MHz 精確的可調(diào)環(huán)路帶寬；支持USB3.0、SATA 6G和PCIe3.0中24MHz帶寬抖動(dòng)傳遞函數(shù)(JTF)測(cè)試

• 精確、可調(diào)、自檢測(cè)和顯示的PLL 環(huán)路帶寬、peaking 和抖動(dòng)傳遞函數(shù)(JTF)- 能夠得到標(biāo)準(zhǔn)要求的“黃金鎖相環(huán)"

• 可調(diào)的峰值、一階或二階滾降能力

• 通過(guò)USB 接口同BERTScope 集成在一起；或者單獨(dú)使用，提供PC 遠(yuǎn)控軟件

• DC 耦合的數(shù)據(jù)通路提供了精確的信號(hào)完整性

• 輸出全速率或分頻時(shí)鐘。全速率時(shí)鐘輸出14.3Gb/s，半速率時(shí)鐘輸出從14.3Gb/s 到17.5Gb/s 和28.6Gb/s

• 內(nèi)建均衡器能夠從帶有嚴(yán)重ISI 數(shù)據(jù)中恢復(fù)時(shí)鐘

• 數(shù)據(jù)測(cè)量能力

• 邊沿密度測(cè)量：確定被測(cè)信號(hào)的邊沿密度

• SSC(擴(kuò)頻時(shí)鐘)波形、dF/dt 的觀測(cè)

• 適合測(cè)試帶有大的頻率偏移的SSC 應(yīng)用

• 可選的直接抖動(dòng)頻譜分析，通過(guò)USB 接口在PC 上提供單獨(dú)的分析軟件

• 可選的“頻譜分析"視圖，使用光標(biāo)測(cè)量抖動(dòng)幅度和頻率

• 用戶可設(shè)定測(cè)量抖動(dòng)頻率限定，進(jìn)行帶限的抖動(dòng)分析

• 預(yù)設(shè)PCI Express Gen2 抖動(dòng)頻率限定

• 可選的PCIe 2.5 、5和8Gb/s PLL 環(huán)路分析(需要抖動(dòng)分析選件)

• CR175A和CR286A提供可選HS(高靈敏度輸入)的可以為幅 度小于40mV(單端)、20mV(差分)信號(hào)s 提供時(shí)鐘恢復(fù)- 這 個(gè)選件沒(méi)有DC 耦合的數(shù)據(jù)通路

Main features and advantages

Instrument-level clock recovery equipment

Continuously adjustable clock recovery from 150Mb/s to 28.6gb /s, covering next-generation IO standards including PCIe3.0, 10gbase-kr, 16xFC, 25/28g CEI and 100gbase-lr-4/100gbase-er-4

Accurate adjustable loop bandwidth from 100KHz to 12MHz; Support USB3.0, SATA 6G and PCIe3.0 24MHz bandwidth jitter transfer function (JTF) test

Precise, adjustable, self-detecting and displaying PLL loop bandwidth, peaking and jitter transfer functions (JTF)

Adjustable peak, first - or second-order roll - down capability

Integrated with BERTScope via USB interface; Or use alone, provide PC remote control software

Dc-coupled data paths provide precise signal integrity

Output full speed or frequency division clock. Full rate clock output is up to 14.3Gb/s, while half rate clock output ranges from 14.3Gb/s to 17.5Gb/s and 28.6Gb/s

The built-in equalizer can recover the clock from severe ISI data

Data measurement capability

Edge density measurement: to determine the edge density of the measured signal

SSC(spread spectrum clock) waveform, dF/dt observation

Suitable for testing SSC applications with large frequency offset

Optional direct jitter spectrum analysis, through the USB interface on PC to provide a separate analysis software

Optional "spectrum analysis" view, using cursor to measure jitter amplitude and frequency

The user can set the limit of measurement jitter frequency and carry out bａnd limit jitter analysis

Preset PCI Express Gen2 jitter frequency limit

Optional PCIe 2.5, 5 and 8Gb/s PLL loop analysis (jitter analysis option required)

CR175A and CR286A provide optional HS(high sensitivity input), which can provide clock recovery for signals with amplitudes less than 40mV(single terminal) and 20mV(differential) s - this option has no dc-coupled data path